Various mechanisms exist for power management of a platform. Existing approaches rely on adjusting processor frequency based on processor utilization. In computer systems using adaptive power management policies, the processor performance state (P-State) adjusts based on demand. As the processor utilization decreases, the processor may transition to a lower performance state to conserve power. As the processor utilization increases, the processor may transition to a higher performance state and may consume more power. In many operating systems, the target performance level, or P-State selection, is based on the combination of processor utilization and the effective P-State as determined by the GV3 Hardware Feedback using the IA32_APERF and IA32_MPERF machine status registers (MSRs). The IA32-APERF/IA32-MPERF ratio, returned in the GV3 Hardware Feedback, provides an effective P-State over the last accounting period by dividing the actual frequency clock count by the maximum frequency clock Count while the core is executing (in C0 C-state).
In most processors, for instance available from Intel Corp., the P-States are coordinated among multiple cores in the processor. If one core is 100% busy and selects the highest frequency to run, the other cores in the same processor also run at the higher frequency. Because the cores are coordinated, the GCV Hardware Feedback provided by the IA32_APERF and IA32_MPERF MSRs may be combined to find the effective frequency of the core, instead of merely using the last P-State, to more accurately select the new target P-state.